parallel instruction execution造句

Parallel instructions execution requires multiple simultaneous L1 D-cache accesses.
The hardware tracing modules ( ETM and ETB ) are compatible, but updated, versions of those used in the ARM9 . In particular, trace semantics were updated to address parallel instruction execution and data transfers.
""'Superscalar processor " "'architecture allows simultaneous parallel instructions execution ( taking advantage of the intrinsic parallelism in the instruction " stream / out of order " by using the " Register renaming " technique for synchronization and reorder of the results.
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